One of the most remarkable aspects of IEDM was the absence of papers describing production 22nm and 20nm manufacturing. As it turns out, Intel decided to delay publication to separately announce their novel 3-dimensional FinFET transistor architecture for 22nm. Instead of having the channel sandwiched between the gate top and the silicon bottom , the tri-gate transistor wraps the gate around three sides, with the silicon underneath. Early research often focused on a double gate FinFET, where the gate is on the sides of the channel, but not the top.
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One of the most remarkable aspects of IEDM was the absence of papers describing production 22nm and 20nm manufacturing. As it turns out, Intel decided to delay publication to separately announce their novel 3-dimensional FinFET transistor architecture for 22nm. Instead of having the channel sandwiched between the gate top and the silicon bottom , the tri-gate transistor wraps the gate around three sides, with the silicon underneath.
Early research often focused on a double gate FinFET, where the gate is on the sides of the channel, but not the top. To avoid confusion and do a bit of marketing , Intel refers to their design as a tri-gate transistor, although it is a type of FinFET. In a conventional planar transistor , the current flowing through the channel is closely related to the width W of the device, divided by the length L effective.
As the industry scales to smaller nodes, it is ideal to decrease L effective , which improves the drive strength of the transistor. However, shorter transistors have less control over the channel and exponentially higher sub-threshold leakage. To control leakage, the channel is heavily doped, which makes everything more susceptible to variability particularly random dopant fluctuations. Variability is one of the biggest 22nm challenges for the industry.
In a tri-gate transistor, the gate surrounds the channel on all three sides and has much better control so that all the charge below the transistor is removed i.
The stronger control decreases sub-threshold leakage, so the transistor is much better at shutting off. This reduces or eliminates dopant variability as well, because less or no doping is needed to control the channel.
However, variation in the height and width of the tri-gate is now an issue, and needs to be tightly controlled.
Additionally, the width W effective of a tri-gate transistor is the sum of all three sides — twice the fin height plus the fin width. To build transistors with different performance and leakage, multiple fins are ganged together and share a single gate — essentially multiplying the width; the gate length can also be adjusted. For future scaling, the height of the fin can be increased to maintain performance.
Intel reported a substantially steeper sub-threshold slope the slope from 0V to 0. The sub-threshold slope measures how fast the device can switch from off to on — a key element of performance.
This is a significant benefit that Intel can harness to improve frequency, active power, idle power or a combination of the three. While higher frequency is great for improving CPU performance, it is not always the best choice. For scenarios where active power is most critical, the 22nm process can keep the same frequency but lower the operating voltage e. Similarly, transistors could use this headroom to significantly lower leakage power for always-on circuits, instead of changing frequency or active power.
While Intel did not cite any specific numbers, it seems likely that an improvement of orders of magnitude is realistic given the exponential relationship between leakage and drive currents. The tri-gate transistors are a tremendous breakthrough in performance and the 22nm process also improves density by the traditional 2X.
But it is important to realize that the performance gains Intel is citing are not simultaneous. Mark Bohr and Bill Holt are responsible for development and manufacturing at Intel, respectively. Along with the research group, their teams spent many years examining the technology options and now ramping tri-gate into high volume production. As part of their presentation, they explained the technology options and rationale behind their decision.
The three transistor options that Intel evaluated at 22nm were conventional planar, tri-gate and fully depleted silicon-on-insulator FD-SOI, sometimes referred to as extremely thin SOI. Scaling bulk transistors to 22nm was the low-risk fallback plan. It is known to work, but with much smaller performance gains and complications from variation.
FD-SOI has very similar benefits to a tri-gate device, but is planar. One advantage is that FD-SOI is compatible with body-biasing techniques, which can improve performance.
Despite this, there are significant challenges; as with all SOI, it is very hard to build diodes for static electricity protection — the oxide layer must be removed.
More importantly, it is very expensive. RWT on Twitter Vendors brag about the transistor count of their design. In this article we discuss system power delivery go… about 3 weeks ago Power delivery is one of the most significant challenges in modern processors.
Intel announces tweaks to 22FFL process for RF, MRAM at IEDM18
At IDF , Mark Bohr, senior research fellow and super-boffin, detailed how Intel has expanded the range of transistor types for each manufacturing process - some are designed for high-power, some for lower-power, lower-leakage, and some use qualities inherent in both. These enable them to be used in a wider range of products, clearly. Coming back to high performance, Intel's Ivy Bridge microarchitecture, the codename for the next-generation chips, has been pushed back a little on the latest roadmap. The current news is that we'll see chips based on the technology come to the market in H1 , which is some six months later than was mooted at last year's IDF. Ivy Bridge chips will use transistors produced on a 22nm process. Now, moving to a smaller process, whereby you fit more transistors for a given size, leads to inexorable problems associated with leakage current.
Intel Defines 22nm Innovation with '3D' Tri-Gate Transistors
The IT industry loves the concept of "innovation," but many vendors' hearts largely belong to just the most conventional sorts of wisdom. That adoration takes a number of shapes: Stone Age business models; dusty Neolithic technologies and architectures; fossilized go-to-market strategies. In point of fact, such vendors are more similar to staid industries and companies, where dependability trumps progress, than they might like to think. I was considering this on May 4th when Intel announced the next "tick" of its continuing "tick-tock" development evolution -- upcoming Ivy Bridge chips that will mark the industry's first 22nm production and the first commercial use of the company's Tri-Gate "3D" technologies. The Tri-Gate manufacturing process forms conducting channels on three sides of a vertical "fin" structure on the silicon substrate. This is in contrast to traditional "2D" planar bulk and partially depleted transistors and fully depleted silicon on insulator FD SOI technologies.
Intel’s 22nm Tri-Gate Transistors
The first I had planned to cover the two papers in one article, but it expanded to the point where it made more sense to split it into two parts. The basic process details as stated at TMD were:. The logic transistor images shown at IEDM17 indicate that 22FFL is based on the nm technology, since we no longer have the tapered fins, and the punch-stop seal is present:.
Intel Announces first 22nm 3D Tri-Gate Transistors, Shipping in 2H 2011